The main RX/TX board of the QRP2001 needs a VFO signal at twice the frequency to be received or transmitted. In order to drive the VFO input circuitry correctly, a signal level of about 2 - 3 volts peak-to-peak is needed. Warning - a VFO level of greater than 5v ptp could damage the main board VFO input circuit.
2 - 3 volts ptp would correspond to +13dBm if the VFO was driving a 50 Ohm load, but the QRP2001 input circuit presents a much higher impedance (several hundred ohms depending on the exact type of logic device fitted and the frequency). Consequently VFO drive requirements are not too onerous.
The Tayloe product detector within the QRP2001 needs two signals in accurate phase quadrature to achieve good rejection of the unwanted sideband. The main board includes circuitry to derive two signals with the required quadrature relationship by dividing down the VFO input signal - which is why the VFO must run at twice the required frequency. However, this circuit only maintains accurate phase quadrature if the VFO signal has an equal mark:space ratio. If the VFO is generating a sine-wave, then the main board also includes signal conditioning circuitry which can produce a square wave with the necessary mark:space ratio from it. However, if the VFO generates a square wave, then this circuitry is not very effective, and it is essential that the VFO itself provides an even mark:space ratio.
The final point to note is that, like all good receivers, the performance of the Tayloe product detector is generally determined by the quality of VFO signal. In particular, it is just as important to maintain a low level of VFO phase noise with this design as it is with more conventional mixers.
Most constructors have their own favourite tried-and-trusted VFO designs. We have tried to make it easy to use such circuits with the QRP2001, rather than specifying a particular VFO circuit. However, the rest of this section outlines three possible VFOs for use with the QRP2001.
This circuit shows a rather trivial example of a single band VFO based around the Clapp design. Since this is isn't intended to be a tutorial in analogue VFO design, and there are many references which cover the subject far better than we could hope to, we haven't made any attempt to optimise this curcuit. It was built in about an hour entirely from bits from a junk-box, and its performance is everything that you would expect under those circumstances!
The actual Clapp oscillator is formed by Q1. The tuned circuit components (left hand of diagram) were chosen to tune roughly 7MHz to 7.6MHz. After this is divided by two within the QRP2001 (see above) it nicely covers the 80m band. In our prototype the basic oscillator was found to give insufficient drive for the QRP2001, so a simple gain stage (Q2) was inserted before the output buffer (Q3).
The 1nF capacitors around the base of Q1 should theoretically be nearer to 500pf, but 1nf was available in the junk box, and seemed to work fine. The preset pot between Q2 and Q3 sets the DC level on the output. About 2.5V worked best on the prototype, but the exact value can be fine tuned to give best rejection of the unwanted sideband in the completed radio. Note that the VFO was powered from the 12V rail within the QRP2001.
If the mechanical construction is given sufficient attention, and with even more careful attention to thermal considerations (to minimise drift) this would probably provide adequate performance for a single-band design. However, as hinted above, this design really is only intended as an example: if you plan to use a 'simple' single-band VFO there are much better designs in the RSGB or ARRL handbooks.
As can be seen from the circuit diagram, this DDS-based design is still a fairly simple circuit. Here's a picture of one of our prototypes.
The design consists of a single AD9851 DDS chip from Analog Devices, and a low-pass filter taken directly from their application notes. The reference frequency is provided by a 30MHz 'canned oscillator', and we use the internal x6 clock multiplier of the AD9851 to create an effective clock rate of 180MHz. With this reference frequency the theoretical output range of the AD9851 is 0 - 90MHz, but of course we use the bottom 60MHz of that range.
Apart from the previously mentioned components and a 5v regulator, you only need a handful of resistors and decoupling capacitors to complete the circuit.
The DDS chip is controlled via a 3-wire interface (data, clock and 'update') from our microprocessor control board.
Both the canned oscillator and the internal clock multiplier contribute to the phase noise on this design, and this is noticable on the QRP2001 in the form of worse noise floor and a significant number of spurious squeeks and whistles. It is possible with some additional complexity to drive the AD9851 directly from a discrete 180MHz oscillator, which does help to clean up the signal to some extent. However this is only a partial solution. If you are interested, a suitable circuit can be found on the Analog Devices web site.
Despite its performance limitations, this simple VFO represents a very usable oscillator, giving complete general coverage of the HF bands. However, if you want the best in performance then the next VFO option represents a more comprehensive solution.
This design provides a TTL-compatible output over the range 0 - 60MHz (resulting in receiver coverage of 0 - 30MHz) with very low phase noise and negligible spurs. However, it is quite a complex circuit and unless you are a pretty experienced constructor we recommend that you get your QRP2001 working with one of the simpler VFOs before tackling this.
We have not presented the complete circuit diagram here, because the design is based around a commercial kit which was available from Kent Electronics until very recently. In keeping with Sod's law, shortly after we had written up this design Kent discontinued the kit! However, we are told that PCBs are still available from another source, so watch this space for further information.
Setting aside such minor glitches, the kit implemented a design by the legendary Klaas Spaargaren, PA0KSB which can be built to cover either 12 - 39MHz or 40 - 80MHz. We use the latter version, with some trickery to give complete HF coverage.
In its basic form, the PA0KSB design covers 40 - 80MHz with enough output level to drive the QRP2001 input stages directly (we only need to add a little bias via a couple of resistors to get the DC levels correct). Since the VFO frequency is effectively halved by the QRP2001 drive circuits, this offers coverage of 20 - 40MHz. However, the phase-locked loop (PLL) within this design uses a binary ripple counter in the feedback loop. By selecting different outputs from the counter, we can pick off a signal in the range of 20 - 40MHz, or 10 - 20MHz...and so on.
Since the PLL has a range of a full octave, and we can select any octave below that from the counter, we can (in theory) generate any frequency up to 40MHz. In practice, there is a lower frequency limit imposed by the finite number of stages in the ripple counter, but this is not a serious limitation. The difficult part is working out, for a given frequency, which output of the counter you need to select in combination with which VFO frequency. This is where our DDS control board comes into play - all of this decision-making and calculation is carried out automatically, and the resulting combination of VFO, octave selection switch and control board gives seamless and transparent coverage of all HF bands.
We can't believe that this is a new idea, but so far we have not come across this approach in any other transceiver, either amateur or professional. Please let us know if we have just re-invented the wheel, because we would love to see how others have tackled some of the design issues! Anyway, the end result is extremely effective, and adds minimal hardware complexity to the PA0KSB design. The only down side occurs when crossing an octave boundary: there is a very short but inevitable glitch as the PLL swings from one extreme of its tuning range to the other. The effect of this is minimised in our design by simply chosing the octave limits to always fall outside the amateur bands.
The block diagram shows how little extra hardware is required to achieve full-range coverage. Note that the PA0KSB design includes its own control circuit based on the (much smaller) PIC 16F84 microcontroller. We simply don't bother to populate that area of the board, and connect the DDS control inputs through a TTL buffer directly to our own control board.
Apart from the change of control circuitry, all that we have added to the kit is a 74LS244 buffer (see warning below), and a 1-of-8 multiplexer to select the required octave.
Warning: we found to our cost that the TTL buffer stage is important to protect the sensistive input pins of the DDS chip. The power supply rails on the control board and DDS board inevitably power up and down at different speeds: if the control board is still powered while the DDS board is not then the DDS input lines are effectively above Vcc, and the DDS chip can be damaged.
The 1-of-8 multiplexer requires some explanation. We tried various parts in this role, but found that the 74FST3253 bus switch, as used in the Tayloe mixer, performed best. The 74FST3253 is actually a dual 1-of-4 device, but here we connect the outputs from both halves of the chip together, and only enable one half at a time, to effectively achieve 1-of-8 functionality. The BC549 transistor is a simple inverter to ensure that when one half of the chip is enabled, the other is disabled...and vice-versa.
The top octave output is taken directly from the buffered 50 Ohm output of the PA0KSB VFO, rather than from the divider. This means that the top octave is not at TTL levels, unlike all of the others. The capacitor and preset pot to the left of the 74FST3253 in the diagram allows adjustment of the DC level on the top octave signal so that it drives the QRP2001 main board properly. Whilst this is a very messy arrangement, all of the countless other ideas which we tried were found to degrade the signal quality too much. We are still looking for a neater solution to this problem, although the arrangement shown here certainly works well.
The DDS board from our prototype can be seen in this picture, which clearly shows where the PIC controller components have been omitted from our version. Also note the addition of the 74LS244 buffer on the left of the picture. This picture shows the other side of our prototype, which is the PLL and VCO board. Again, note the little board to the right of the picture which holds the 1-of-8 octave selector circuit (the metal-can transistor on that board is a hangover from an earlier design, and is not part of the final version).
So, the steps involved in building this VFO are:
1) Buy the PCBs for the PA0KSB DDS design (source TBA!)
2) Build the VCO/PLL board as described
3) Build just the DDS and low-pass filter parts of the DDS/Control board (see earlier photo)
4) Interface the 3 DDS control lines to our Control Board via a 74SN244 buffer (see block diagram)
5) Take VFO output and 7 lower octave outputs via 1-of-8 selector (see block diagram) to get a frequency range of 8 octaves
6) Feed output of 1-of-8 selector to QRP2001 VFO input
During testing we discovered a few features of the PA0KSB design which it's worth noting. The VCO uses a BB212 varicap which is an obsolete device. Kent Electronics can supply a very close equivalent, but ours did not have quite such a wide capacitance range as a real BB212. To achieve a full octave of coverage we had to increase the fixed capacitor in series with the varicap from 47pf to 56pf. Secondly the VCO control voltage is provided by an op-amp fed from a 10v rail, and the op-amp output could only just get up to the 8v value needed for the highest frequencies in each octave. This made the design very slow to retune when crossing octave boundaries. A much better result was obtained by replacing the 10v regulator with a low drop-out 12v regulator, and ensuring that the QRP2001 was powered by a PSU giving at least 13v. Finally, the feedback loop in the PLL includes a resistor (R55 in the PA0KSB design) which is selected during testing for best compromise between capture time and loop stability. In practice we found that you can appear to have a stable PLL only to find when you connect it to the mixer that it sounds terrible. After much fiddling with resistor values we replaced R55 with a 1K miniature preset...and wished that we had done so much sooner!
